Leading Zero Anticipation and Detection-A Comparison of Methods
نویسندگان
چکیده
Design of the leading zero anticipator ( L a ) or detector (LZD) is pivotal to the normalization of results for addition and fused multiplication-addition in highperjormance floating point processors. This paper formalizes the analysis and describes some alternative organizations and implementations from the known art. It shows how choices made in the design are o fen dependent on the overall design of the addition unit, on how subtraction is handled when the exponents are the same, and on how it detects and corrects for the possible one-bit error of the 15%.
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